MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 353

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Read: Anytime
Write: See each bit description
PHYADD[4:0] — EPHY Address for MII Requests
12.3.2.3 Ethernet Physical Transceiver Status Register (EPHYSR)
Read: Anytime
Write: See bit descriptions
10DIS — EPHY Port 10BASE-T mode status
EPHYIF — EPHY Interrupt Flag
Freescale Semiconductor
100DIS — EPHY Port 100BASE-TX mode status
These bits can be written anytime, but the EPHY address is latched to the MII PHY address register
(MII address 21.4:0) only when the EPHYEN bit transitions from 0 to 1. PHYADD4 is the MSB of
the of the EPHY address.
This bit is not writable — read only. Output to indicate EPHY port Base100-TX mode status.
This bit is not writable. Output to indicate EPHY port 10BASE-T mode status.
EPHYIF indicates that interrupt conditions have occurred. To clear the interrupt flag, write a 1 to this
bit after reading the interrupt control register via the MII management interface.
1 = EPHY port 100BASE-TX disabled
0 = EPHY port 100BASE-TX enabled
1 = EPHY port 10BASE-T disabled
0 = EPHY port 10BASE-T enabled
1 = EPHY interrupt has occurred
0 = EPHY interrupt has not occurred
Module Base + $2
RESET:
W
R
Figure 12-5. Ethernet Physical Transceiver Status Register (EPHYSR)
7
0
0
= Unimplemented or Reserved
6
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
100DIS
5
1
10DIS
4
1
3
0
0
2
0
0
Memory Map and Register Descriptions
1
0
0
EPHYIF
0
0
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