MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 448

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 17 Background Debug Module (BDMV4)
17.3.2.1
Note:
1
2
Read: All modes through BDM operation
Write: All modes but subject to the following:
448
Special single-chip mode:
Special peripheral mode:
BDMACT
ENBDM is read as "1" by a debugging environment in Special single-chip mode when the device is not secured or secured
but fully erased (Flash and EEPROM).This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
UNSEC is read as "1" by a debugging environment in Special single-chip mode when the device is secured and fully erased,
else it is "0" and can only be read if not secure (see also bit description).
ENBDM
•
•
•
•
Field
7
6
BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the
standard BDM firmware lookup table upon exit from BDM active mode.
CLKSW can only be written via BDM hardware or standard BDM firmware write commands.
All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
ENBDM should only be set via a BDM hardware command if the BDM firmware commands are
needed. (This does not apply in special single-chip mode).
All other modes:
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secure mode, this
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
BDM Status Register (BDMSTS)
Reset:
bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete.
W
R
ENBDM
1
7
0
0
0
1
Figure 17-3. BDM Status Register (BDMSTS)
= Unimplemented or Reserved
Table 17-2. BDMSTS Field Descriptions
BDMACT
1
1
1
0
MC9S12NE64 Data Sheet, Rev. 1.1
6
ENTAG
5
0
0
0
0
Description
SDV
0
0
0
0
4
TRACE
3
0
0
0
0
= Implemented (do not alter)
CLKSW
0
0
0
0
2
Freescale Semiconductor
UNSEC
0
1
0
0
0
2
0
0
0
0
0
0