MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 117
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MC9S12NE64VTU
Manufacturer Part Number
MC9S12NE64VTU
Description
IC MCU 25MHZ ETHERNET/PHY 80TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64VTU
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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3.3.2.2.3
Read:Anytime.
Write:Anytime.
This register configures each port S pin as either input or output.
If the SPI is enabled, the SPI controls the SPI related pins (SPI_SS, SPI_SCK, SPI_MOSI, SPI_MISO)
I/O direction, and the corresponding DDRS[7:4] bits have no effect on the SPI pins I/O direction. Refer to
the SPI block description chapter for details.
When the SCI0 or SCI1 transmitters are enabled, the corresponding transmit pins, SCI0_TxD and
SCI0_TxD, I/O direction is controlled by the SCI0 and SCI1 respectively, and the corresponding DDRS3
and DDRS1 bits have no effect on their I/O direction. When the SCI0 or SCI1 receivers are enabled, the
corresponding receive pins, SCI0_RXD and SCI1_RXD, I/O direction is controlled by the SCI0 and SCI1
respectively, and the DDRS2 and DDRS0 bits have no effect on their I/O direction. Refer to the SCI block
description chapter for further details.
The DDRS[7:0] bits revert to controlling the I/O direction of the pins when the associated SPI or SCI
function is disabled.
DDRS[7:0] — Data Direction Port S
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS
or PTIS registers, when changing the DDRS register.
3.3.2.2.4
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port S output pin as either full or reduced. If the port is
used as input this bit is ignored.
Freescale Semiconductor
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Module Base + $A
Module Base + $B
Reset:
Reset:
Read:
Read:
Write:
Write:
Data Direction Register (DDRS)
Reduced Drive Register (RDRS)
DDRS7
RDRS7
Bit 7
Bit 7
0
0
DDRS6
RDRS6
Figure 3-11. Port S Reduced Drive Register (RDRS)
Figure 3-10. Port S Data Direction Register (DDRS)
6
0
6
0
MC9S12NE64 Data Sheet, Rev. 1.1
DDRS5
RDRS5
5
0
5
0
DDRS4
RDRS4
4
0
4
0
DDRS3
RDRS3
3
0
3
0
DDRS2
RDRS2
2
0
2
0
Memory Map and Register Descriptions
DDRS1
RDRS1
1
0
1
0
DDRS0
RDRS0
Bit 0
Bit 0
0
0
117
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