MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 344

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 11 Ethernet Media Access Controller (EMACV1)
11.4.6.2 Read Operation
To perform a read operation through MII management, the OP field in MCMST must be written to 10 while
the BUSY bit is clear. The PADDR field in MPADR indicates which PHY device is addressed and the
RADDR in MRADR indicates which 16-bit register is read from the PHY device. The MII management
creates an MII management frame and serially shifts it out to the PHY through the MII_MDIO pin. After
the turnaround field, the PHY serially shifts the register data from the PHY to the EMAC through the
MII_MDIO pin. After the read MII management frame operation has completed, the BUSY bit clears, the
MRDATA register is updated, and the MMCIF bit in IEVENT is set. If not masked (MMCIE in IMASK
is set), an MII management transfer complete interrupt is pending while this flag is set.
11.4.6.3 Write Operation
To perform a write operation through MII management, the OP field in MCMST must be written to 01
while the BUSY bit is clear. The PADDR field in MPADR indicates which PHY device is addressed and
the RADDR bit in MRADR indicates which 16-bit register is read from the PHY device. The MII
management creates an MII management frame and serially shifts it out to the PHY through the
MII_MDIO pin. After the turnaround field, the MWDATA register is serially shifted to the PHY through
the MII_MDIO pin. After the write MII management frame operation has completed, the BUSY bit is
cleared and the MMCIF bit in IEVENT is set. If not masked (MMCIE in IMASK is set), an MII
management transfer complete interrupt is pending while this flag is set.
11.4.7
The MII transmit data stream is internally looped back as an MII receive data stream if the MLB bit is set.
The MII_TXCLK and MII_RXCLK are internally driven from the system clock. MII_RXD is driven from
MII_TXD. MII_RXDV is driven from MII_TXEN. MII_RXER is driven from MII_TXER. The
344
MDIO
MDC
(MAC)
MDIO
MDIO
MDC
(PHY)
(MAC)
Preamble
32 1s
Optional
Preamble
Optional
32 1s
Loopback
z
0 1 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0
Start Opcode
0 1 1 0 0 1 1 1 0 0 0 0 0 1
Start Opcode
(Write)
(Read)
(PHYAD = 0Eh)
(PHYAD = 0Eh)
PHY Address
Figure 11-27. Typical MDC/MDIO Write Operation
Figure 11-26. Typical MDC/MDIO Read Operation
PHY Address
MC9S12NE64 Data Sheet, Rev. 1.1
Register Address
(REGAD = 01h)
Register Address TA
(REGAD = 01h)
z
z
TA
0
0 0 1 1 0 0 0
Register Data
Register Data
0
1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 z
Freescale Semiconductor
0
z
Idle
Idle
z
z