MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 384

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
13.4.3 POR - Power-On Reset
This functional block monitors output VDD. If V
exceeds V
sequence.
Due to its role during chip power-up this module must be active in all operating modes of
VREG_PHY.
13.4.4 LVR - Low Voltage Reset
Block LVR monitors the primary output voltage V
signal LVR asserts and when rising above the deassertion level (V
The LVR function is available only in Full Performance Mode.
13.4.5 CTRL - Regulator Control
This part contains the register block of VREG_PHY and further digital functionality needed to
control the operating modes. CTRL also represents the interface to the digital core logic.
13.5 Resets
13.5.1 General
This section describes how VREG_PHY controls the reset of the MCU.The reset values of
registers and signals are provided in Section 13.3, “Memory Map and Registers.” Possible reset
sources are listed in Table 13-2.
13.5.2 Description of Reset Operation
13.5.2.1 Power-On Reset
During chip power-up the digital core may not work if its supply voltage V
deassertion level (V
reset is kept high until V
the device continues the start-up sequence. The power-on reset is active in all operation modes of
VREG_PHY.
384
PORD
, the signal goes low. The transition to low forces the CPU in the power-on
PORD
DD
). Therefore signal POR which forces the other blocks of the device into
Table 13-2. VREG_PHY - Reset Sources
exceeds V
Low Voltage Reset
Power-on Reset
Reset Source
MC9S12NE64 Data Sheet, Rev. 1.1
PORD
. Then POR becomes low and the reset generator of
DD
DD
available only in Full
Performance Mode
. If it drops below the assertion level (V
is below V
Local Enable
always active
PORD
LVRD
, signal POR is high, if it
) signal LVR negates again.
DD
Freescale Semiconductor
is below the POR
LVRA
)