MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 325

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

BUSY — Operation in Progress
NOPRE — No Preamble
MDCSEL — Management Clock Rate Select
Freescale Semiconductor
This read-only status bit indicates MII management activity. BUSY is asserted after a valid OP write
and is cleared when the MMCIF flag is set.
Any value written while BUSY is set is ignored. The IEEE 802.3 standard allows the preamble to be
dropped if the attached PHY does not require it. While this bit is set, a preamble is not prepended to
the MII management frame.
Any value programmed while BUSY bit is set is ignored. This field controls the frequency of the MII
management data clock (MDC) relative to the IP bus clock. MDC toggles only during a valid MII
management transaction. While MDC is not active, it remains low. Any nonzero value results in an
MDC frequency given by the following formula:
MDC frequency = Bus clock frequency / (2 * MDCSEL)
The MDCSEL field must be programmed with a value to provide an MDC frequency of less-than or
equal-to 2.5 MHz to be compliant with the IEEE MII specification. The MDCSEL must be set to a
nonzero value in order to source a read or write MII management frame.
1 = MII is busy (operation in progress).
0 = MII is idle (ready for operation).
1 = No preamble is sent.
0 = 32-bit preamble is sent.
IP Bus Clock Frequency
20 MHz
25 MHz
33 MHz
40 MHz
50 MHz
Table 11-6. Programming Examples for MDCSEL
Table 11-5. MII Management Frame Operation
BUSY
1
0
0
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
OP
00
01
10
11
xx
MDCSEL
0xA
0x4
0x5
0x7
0x8
Operation
Ignore
Ignore
Ignore
Write
Read
MDC Frequency
Memory Map and Register Descriptions
2.36 MHz
2.5 MHz
2.5 MHz
2.5 MHz
2.5 MHz
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