MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 52

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 1 MC9S12NE64 Device Overview
1.2.3.28 PH5 / KWH5 / MII_TXEN — Port H I/O Pin 5
PH5 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
transmit enabled (MII_TXEN) signal. It can be configured to generate an interrupt (KWH5) causing the
MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH5 pin is configured as
a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
1.2.3.29 PH4 / KWH4 / MII_TXCLK — Port H I/O Pin 4
PH4 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
transmit Clock (MII_TXCLK) signal. It can be configured to generate an interrupt (KWH4) causing the
MCU to exit stop or wait mode. While in reset and immediately out of reset, the PH4 pin is configured as
a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
1.2.3.30 PH3 / KWH3 / MII_TXD3 — Port H I/O Pin 3
PH3 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
transmit data (MII_TXD3) signal. It can be configured to generate an interrupt (KWH3) causing the MCU
to exit stop or wait mode. While in reset and immediately out of reset, the PH3 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
1.2.3.31 PH2 / KWH2 / MII_TXD2 — Port H I/O Pin 2
PH2 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
transmit data (MII_TXD2) signal. It can be configured to generate an interrupt (KWH2) causing the MCU
to exit stop or wait mode. While in reset and immediately out of reset, the PH2 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
1.2.3.32 PH1 / KWH1 / MII_TXD1 — Port H I/O Pin 1
PH1 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
transmit data (MII_TXD1) signal. It can be configured to generate an interrupt (KWH1) causing the MCU
to exit stop or wait mode. While in reset and immediately out of reset, the PH1 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
1.2.3.33 PH0 / KWH0 / MII_TXD0 — Port H I/O Pin 0
PH0 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
transmit data (MII_TXD0) signal. It can be configured to generate an interrupt (KWH0) causing the MCU
to exit stop or wait mode. While in reset and immediately out of reset, the PH0 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
MC9S12NE64 Data Sheet, Rev 1.0
52
Freescale Semiconductor