MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 116

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.2
3.3.2.2.1
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SPI function takes precedence over the general-purpose I/O function if the SPI module is enabled. If
the SPI is enabled the PS[7:4] pins become SPI_SS, SPI_SCK, SPI_MOSI, and SPI_MISO, and their
configuration is determined by several status bits in the SPI module. Refer to the SPI block description
chapter for details.
The SCI1 and SCI0 function take precedence over the general-purpose I/O function on pins PS[3:0]. If the
SCI1 or SCI0 transmitters or receivers are enabled, the SCI1 and SCI0 transmit pins, SCI1_TXD and
SCI0_TXD, are configured as outputs if the corresponding transmitter is enabled. The SCI1 and SCI0
receive pins, SCI1_RXD and SCI0_RXD, are configured as inputs if the corresponding receiver is enabled.
Refer to the SCI block description chapter for details.
3.3.2.2.2
Read:Anytime.
Write: writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
116
Module Base + $8
Module Base + $9
Reset:
Reset:
Read:
Read:
Write:
Write:
SPI
SCI
Port S Registers
I/O Register (PTS)
Input Register (PTIS)
PTIS7
PTS7
Bit 7
Bit 7
SS
—
—
0
= Reserved or unimplemented
PTIS6
PTS6
SCK
—
—
6
0
6
Figure 3-9. Port S Input Register (PTIS)
Figure 3-8. Port S I/O Register (PTS)
MC9S12NE64 Data Sheet, Rev. 1.1
PTIS5
MOSI
PTS5
—
—
5
0
5
PTIS4
PTS4
MISO
—
—
4
0
4
SCI1_TXD SCI1_RXD SCI0_TXD SCI0_RXD
PTIS3
PTS3
—
—
3
0
3
PTIS2
PTS2
—
—
2
0
2
PTIS1
PTS1
—
—
1
0
1
Freescale Semiconductor
PTIS0
PTS0
Bit 0
Bit 0
—
—
0