MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 124

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 3 Port Integration Module (PIM9NE64V1)
This register always reads back the status of the associated pins. This can be also used to detect overload
or short circuit conditions on output pins.
3.3.2.4.3
Read:Anytime.
Write:Anytime.
This register configures each port H pin as either input or output.
DDRH[6:0] — Data Direction Port H
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTH
or PTIH registers, when changing the DDRH register.
If the EMAC MII external interface is enabled, pins PH[6:0] become MII_TXER, MII_TXEN,
MII_TXCLK, MII_TXD[3:0]. In that case, DDRH[6:0] bits have no effect on their I/O direction.
3.3.2.4.4
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port H output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRH[6:0] — Reduced Drive Port H
124
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Module Base + $1A
Module Base + $1B
Reset:
Reset:
Read:
Read:
Write:
Write:
Data Direction Register (DDRH)
Reduced Drive Register (RDRH)
Bit 7
Bit 7
—
—
0
0
= Reserved or unimplemented
= Reserved or unimplemented
Figure 3-26. Port H Reduced Drive Register (RDRH)
DDRH6
RDRH6
Figure 3-25. Port H Data Direction Register (DDRH)
6
0
6
0
MC9S12NE64 Data Sheet, Rev. 1.1
DDRH5
RDRH5
5
0
5
0
DDRH4
RDRH4
4
0
4
0
DDRH3
RDRH3
3
0
3
0
DDRH2
RDRH2
2
0
2
0
DDRH1
RDRH1
1
0
1
0
Freescale Semiconductor
DDRH0
RDRH0
Bit 0
Bit 0
0
0