MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 127

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.2.5
3.3.2.5.1
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The EMAC MII external interface and IIC take precedence over general-purpose I/O function. If the
EMAC MII external interface is enabled in external PHY mode, PJ[3:0] pins become MII_MDC,
MII_MDIO, MII_CRS, MII_COL. If IIC is enabled, PJ[7:6] pins become IIC_SDA and IIC_SCL. Please
refer to the EMAC and IIC block description chapters for details.
3.3.2.5.2
Read:Anytime.
Write: writes to this register have no effect.
This register always reads back the status of the associated pins. This can be used to detect overload or
short circuit conditions on output pins.
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EMAC
Reset:
Reset:
Read:
Read:
Write:
Write:
KWU
IIC
Port J Registers
I/O Register (PTJ)
Input Register (PTIJ)
IIC_SCL
PTIJ7
PTJ7
Bit 7
Bit 7
—
—
0
KWJ
= Reserved or unimplemented
= Reserved or unimplemented
IICSDA
PTIJ6
PTJ6
—
—
6
0
6
Figure 3-32. Port J Input Register (PTIJ)
Figure 3-31. Port J I/O Register (PTJ)
MC9S12NE64 Data Sheet, Rev. 1.1
—
—
5
0
5
0
—
—
4
0
4
0
MII_COL
PTIJ3
PTJ3
—
—
3
0
3
MII_CRS
PTIJ2
PTJ2
—
—
2
0
2
Memory Map and Register Descriptions
KWJ
MII_MDIO
PTIJ1
PTJ1
—
—
1
0
1
MII_MDC
PTIJ0
PTJ0
Bit 0
Bit 0
—
—
0
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