MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 335

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.4.2.1 Address Recognition
The EMAC executes filtering by using the destination address of a receive frame and eliminates a frame
that does not satisfy a given condition. See
11.4.2.1.1
If the PROM bit is set, promiscuous mode is enabled and all frames are accepted regardless of address.
The PROM bit does not affect any other filtering in the EMAC.
11.4.2.1.2
Unless the PROM bit is set, the 48-bit MAC address (MACAD) is compared for an exact match with the
destination address of a receive frame with an individual address (group bit is 0). If the unicast address of
the receive frame matches MACAD, the frame is accepted; otherwise, it is rejected.
11.4.2.1.3
A broadcast frame (48-bit address of all 1s) is accepted if the BCREJ bit is 0 and rejected if the BCREJ bit
is 1 unless the PROM bit is set.
11.4.2.1.4
If the CONMC bit is set to 0, all multicast frames are accepted. If the CONMC bit is 1 and the PROM bit
is 0, only multicast frames with the hash table match are accepted.
The hash table algorithm operates as follows. The 48-bit destination address is mapped into one of 64 bits,
which are represented by the 64 bits stored in MCHASH. This mapping is performed by passing the 48-bit
address through the 32-bit CRC generator and selecting the 6 most significant bits of the CRC-encoded
result to generate a number between 0 and 63. If the CRC generator selects a bit that is set in the hash table,
the frame is accepted; otherwise, it is rejected. To set the hash table, the CRC of a multicast address must
be calculated and the corresponding bit must be set in advance.
11.4.2.1.5
If the EMAC is in full-duplex mode and the RFCE bit is set, the receiver detects incoming PAUSE frames.
A PAUSE frame has a 48-bit destination multicast address of 01-80-C2-00-00-01 or unique DA. Upon
detection of a PAUSE frame, the frame is temporarily accepted for further type/length recognition.
Freescale Semiconductor
Promiscuous Mode
Unicast Filter
Broadcast Filter
Multicast Filter
PAUSE Destination Address
MC9S12NE64 Data Sheet, Rev. 1.1
Figure 11-24
for the address recognition algorithm.
Functional Description
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