MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 45

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

orig. order
66
67
68
41
42
10
11
12
13
43
44
14
69
70
61
71
72
73
58
4
3
1
2
5
Freescale Semiconductor
80 Pin
No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
—
—
—
—
—
112 Pin
60–63
77–80
No.
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
64
65
66
67
68
69
70
PHY_VDDTX
PHY_RBIAS
PHY_VDDA
PHY_VSSA
PHY_TXP
Function
VDDPLL
VSSPLL
RESET
PA[7:0]
EXTAL
BKGD
Name
VDD2
TEST
VSS2
XTAL
XFC
PE3
PE2
PE1
PE0
PL6
PL5
PL4
PL3
Pin
1
Table 1-4. Signal Properties (Sheet 3 of 4)
ADDR[15:8]/
DATA[15:8]
Function
COLLED
DUPLED
TAGLO
MODC
Name
XIRQ
R/W
IRQ
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
MC9S12NE64 Data Sheet, Rev 1.0
Function
LSTRB
TAGHI
Name
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
VDDPLL
VDDPLL
VDDPLL
Domain
VDDTX
Power
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PHY_
VSSA
PHY_
PERL/
PERL/
PUCR
PUCR
PUCR
PUCR
PERL/
PERL/
PUCR Disabled
CTRL
PPSL
PPSL
PPSL
PPSL
None
None
None
NA
NA
NA
NA
NA
Internal Pull
Resistor
Disabled Port L I/O pin
Disabled Port L I/O pin
Disabled
Disabled
Reset
State
None
None
NA
NA
NA
NA
NA
Up
Up
Up
Up
Up
External reset pin
See
PLL filter pin
See
Oscillator pins
Port E I/O pin; low
strobe; tag signal
low
Port E I/O pin; R/W
in expanded
modes
Port E input; external
interrupt pin
Port E input;
non-maskable
interrupt pin
Background debug;
mode pin; tag signal
high
Port L I/O pin; EPHY
collision LED
Port L I/O pin; EPHY
full duplex LED
Port A I/O pin;
multiplexed
address/data
See
See
Bias control:1.0%
external resistor
(see the Electricals
Chapter for R
See
See
See
Twisted pair output +
Must be grounded
Description
Table 1-5
Table 1-5
Table 1-5
Table 1-5
Table 1-5
Table 1-5
Table 1-5
Signal Description
Bias
)
Analog
Analog
Output
Output
Reset
State
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
45