T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 99

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
10 Error Reporting and Interrupt Control
10.1 Interrupt Control Registers
10.1.9 Interrupt Servicing Registers
10.1.9.1 Arbitration Control Register
The arbitration control register allows for four modes of interrupt control operation as shown below:
!
!
!
!
Table 84. Arbitration Control Register
10.1.9.2 SYSERR and CLKERR Output Select Register
The SYSERR output select register controls how the SYSERR signal is asserted (active-high level, active-low
level, active-high pulse, or active-low pulse).
The SYSERR pulse-width register controls how wide the SYSERR pulse is (when selected output format = high or
low pulse). Value corresponds to the number of 32.768 MHz periods – 1.
The CLKERR output select register controls how the CLKERR signal is asserted (active-high level, active-low
level, active-high pulse, or active-low pulse).
The CLKERR pulse-width register controls how wide the CLKERR pulse is (when selected output format = high or
low pulse). Value corresponds to the number of 32.768 MHz periods – 1.
Byte Address
Disabled. This mode bypasses any interrupt controller operation. No FG or GP inputs are allowed as external
interrupt inputs. SYSERR assertion is a simple logical OR of the internal system error bits. CLKERR assertion is
a simple logical OR of the internal clock error bits.
Flat. This mode treats all 48 possible inputs (eight from external FG[7:0], eight from external GP[7:0], 16 from
internal system errors, 16 from internal clock errors) with equal weight, and queues them for in-service via a
round-robin arbitration.
Tier, no pre-empting. This mode assigns three priority levels. The highest level is internal clock errors CLK[15:0];
next level is internal system errors SYS[15:0]; lowest level is external errors FG[7:0] and GP[7:0]. Arbitration pri-
ority encodes between the three levels. Multiple interrupts within a level are queued round-robin.
Tier, with pre-empting. This mode is the same as tier, with the added ability to pre-empt a current in-service inter-
rupt according to the three priority levels.
0x00610
Arbitration
Control
Name
Bit(s) Mnemonic
7:0
(continued)
JAMSR
(continued)
0000 0000
0000 0001
0000 0010
0001 0010
Value
Ambassador T8110L H.100/H.110 Switch
Disable interrupt controller (default).
Flat structure (round-robin arbiter).
Tier structure (three levels), no pre-empting.
Tier structure (three levels), pre-empting.
Function
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