T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 69

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.7 Clock Circuit Operation—Fallback and Failsafe
6.7.1 Clock Fallback (continued)
6.7.1.1 H-Bus Clock Enable/Disable on Fallback (continued)
Table 55. H-Bus Clock Enable State Description
H-Bus Clock
Enable State
A_MASTER T8110L clock output control regis-
B_MASTER T8110L clock output control regis-
DIAG_ABC
A_ERROR
B_ERROR
DIAG_AB
C_ONLY
A_ONLY
B_ONLY
INITIAL
Initial condition, waiting for clock
output control register program-
ming.
T8110L is driving all H-bus clocks
(diagnostic mode).
T8110L is driving both the H-bus A
and B clocks (diagnostic mode).
T8110L is driving only the
H-bus C clocks.
ters are programmed to drive A
clocks and C clocks (T8110L is an
A clock master), or T8110L was
supplying a backup A clock and has
been promoted to A clock master.
T8110L clock output control regis-
ters are programmed to drive A
clocks only (T8110L is a B clock
slave, and supplies a backup A
clock).
T8110L has detected a clock error
while driving the A clocks, and has
stopped driving any H bus clocks.
ters are programmed to drive B
clocks and C clocks (T8110L is a B
clock master), or T8110L was sup-
plying a backup B clock and has
been promoted to B clock master.
T8110L clock output control regis-
ters are programmed to drive B
clocks only (T8110L is an A clock
slave, and supplies a backup B
clock).
T8110L has detected a clock error
while driving the B clocks, and has
stopped driving any H bus clocks.
Description
(continued)
A_MASTER A clock error on CT_C8_B or /CT_FRAME_B
B_MASTER A clock error on CT_C8_A or /CT_FRAME_A
other states
A_ERROR A clock error on CT_C8_A or /CT_FRAME_A
A_ERROR A clock error on CT_C8_A or /CT_FRAME_A
B_ERROR A clock error on CT_C8_B or /CT_FRAME_B
B_ERROR A clock error on CT_C8_B or /CT_FRAME_B
Any of the
INITIAL
INITIAL
INITIAL
INITIAL
INITIAL
INITIAL
INITIAL
INITIAL
INITIAL
Exit To
Ambassador T8110L H.100/H.110 Switch
(continued)
User update of the clock output control regis-
ter (0x00220, master output enables).
User update of the clock output control regis-
ter (0x00220, master output enables).
User update of the clock output control regis-
ter (0x00220, master output enables).
User update of the clock output control regis-
ter (0x00220, master output enables).
is detected; disable clock outputs.
User update of the clock output control regis-
ter (0x00220, master output enables).
is detected; promote to A clock master.
is detected; disable clock outputs.
User update of the clock output control regis-
ter (0x00220, master output enables).
User update of the clock output control regis-
ter (0x00220, master output enables).
is detected; disable clock outputs.
User update of the clock output control regis-
ter (0x00220, master output enables).
is detected; promote to B clock master.
is detected; disable clock outputs.
User update of the clock output control regis-
ter (0x00220, master output enables).
User update of the clock output control regis-
ter (0x00220, master output enables).
Exit Condition
69