T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 44

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
6 Clock Architecture
44
SC-BUS (2 CLOCKS)
H-MVIP (4 CLOCKS)
SCSA (2 CLOCKS)
MVIP (2 CLOCKS)
PROGRAMMABLE
INVERSION
/CT_FRAME_A
/CT_FRAME_B
LREF[0:7]
CT_NETREF1
CT_NETREF2
/FR_COMP
LREF[4:7]
CT_C8_A
CT_C8_B
XTAL1 OUT
(FROM XTAL2)
(FROM XTAL1)
LREF[0:7]
OSC1
SELECT
8
CLOCK
4
XTAL1 IN/
OSC1 IN
FRAME
CLK
SEL
SEL
8
CT_NETREF2
CT_NETREF1
INVERSION
PROG.
BY 8
DIV
DIVIDE REGISTER
DIVIDE REGISTER
Figure 5. T8110L Main Clocking Paths
DIVIDE-BY-n
DIVIDE-BY-n
RESOURCE
PROGRAMMABLE
PROGRAMMABLE
Figure 6. T8110L NETREF Paths
INVERSION
INVERSION
MAIN
REF1
REF2
NET-
NET-
SEL
SEL
AND RATE
SOURCE
DPLL1
PRI_REF_OUT
NR1 SOURCE
SELECT
NR2 SOURCE
SELECT
NR1_SEL_OUT
NR2_SEL_OUT
MULT
BY 2
NR1 DIV
NR2 DIV
SELECT
SELECT
DPLL1
4 MHz
BY 4
2 OR
DIV
NR1_DIV_IN
PRI_REF_IN
NR2_DIV_IN
SOURCE
SELECT
CLOCK
FRAME
SYNC
AND RATE
DIVIDE REGISTER
DIVIDE REGISTER
SOURCE
DPLL2
DIVIDE-BY-n
DIVIDE-BY-n
SAFE
FAIL
NETREF1
NETREF2
SAMPLED FRAME
65.536 MHz
APLL1
PROGRAMMABLE
PROGRAMMABLE
or 12 MHz
1, 5, 3, 6,
DPLL2
CONTROLS
INVERSION
INVERSION
BIT SLIDER
BYPASS
APLL1
BYPASS
APLL2
65.536 MHz
GENERATION
PHASE
ALIGNMENT
INTERNAL
CLOCK
CT_NETREF1
CT_NETREF2
49.408 MHz
SELECT
APLL2
APLL2
RATE
Agere Systems Inc.
X4
X8
XTAL2 OUT
February 2004
2.048 MHz
4.096 MHz
8.192 MHz
16.364 MHz
FRAME
32.768 MHz
(INTERNAL)
FRAME
MEMORIES
TO
TCLK_OUT
MUX
OSC2
XTAL2 IN/
OSC2 IN
5-9432 (F)
5-9433 (F)