T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 52

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
6 Clock Architecture
6.1 Clock Input Control Registers
6.1.12 NETREF2 Registers
The NETREF2 input selector, NETREF2 divider, and NETREF2 LREF select registers control the signal paths
used to generate CT_NETREF2 (see Figure 6 on page 44).
Table 45. NETREF2 Registers
* Selection of which LREF is controlled at register 0x00216.
52
Address
0x00214 NETREF2 Input
0x00215 NETREF2 Divider
0x00216 NETREF2 LREF
Byte
Selector
Select
Name
(continued)
Bit(s) Mnemonic
7:4
3:0
7:0
7:0
(continued)
NR2DR
N2DSN
N2LSR
N2ISN
LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256},
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
Value
0000
0001
0000
0001
0010
0100
1000
Divider input = selector output (default).
Divider input = external input NR1_DIV_IN.
Oscillator/XTAL1-div-8, 2.048 MHz (default).
Oscillator/XTAL1, 16.384 MHz.
CT_NETREF1 input.
LREF input*.
Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.
respectively.
Select LREF0 (default).
Select LREF0.
Select LREF1.
Select LREF2.
Select LREF3.
Select LREF4.
Select LREF5.
Select LREF6.
Select LREF7.
Function
Agere Systems Inc.
February 2004