T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 53

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.2 Clock Output Control Registers
The registers listed below control output enable and rate selection of the T8110L clock path outputs.
Table 46. Clock Output Control Register Map
6.2.1 Master Output Enables Register
The master output enables register controls the output enables for H-bus and compatibility clocks (CCLK) for
T8110L clock mastering. A-clocks refers to the combination of CT_C8_A bit clock and /CT_FRAME_A frame refer-
ence.
B-clocks refers to the CT_C8_B bit clock and /CT_FRAME_B frame reference.
These programmable enables are used in conjunction with master enable register 0x00103, H-bus clock enables,
HCKEB.
The NETREF output enables register controls the output enables for CT_NETREF1 and CT_NETREF2. These
programmable enables are used in conjunction with master enable register 0x00103, H-bus clock enables,
HCKEB.
The CCLK output enables register is used in conjunction with register 0x00220 and controls the output enables for
various groupings of compatibility clocks, including the following:
!
!
!
!
!
Address
DWORD
(20 Bits)
0x00220
0x00224
0x00228
H-MVIP bit clock only(/C16±)
MVIP clocks (/C4, C2)
H-MVIP clocks (/C16±, /C4, C2)
SC-bus clocks (SCLK, /SCLKx2)
/FR_COMP compatibility frame reference
SCLK output rate
C8 output rate
L_SC3 select
Byte 3
(continued)
/FR_COMP width
L_SC2 select
TCLK select
Byte 2
NETREF output enables
Register
Ambassador T8110L H.100/H.110 Switch
L_SC1 select
Reserved
Byte 1
Master output enables
CCLK output enables
L_SC0 select
Byte 0
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