T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 6

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
Figure
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. T8110L Clock Fallback States .............................................................................................................. 66
Figure 11. T8110L H-Bus Clock Enable States ..................................................................................................... 68
Figure 12. T8110L Clock Failsafe States ............................................................................................................... 70
Figure 13. FG[7:0] Functional Paths ...................................................................................................................... 77
Figure 14. Frame Group 8 kHz Reference Timing ................................................................................................. 78
Figure 15. GP[7:0] Functional Paths ...................................................................................................................... 82
Figure 16. Local Stream 16.384 Mbits/s Timing..................................................................................................... 86
Figure 17. Local Stream 16.384 Mbits/s Circuit ..................................................................................................... 87
Figure 18. Superrate I/O Configuration .................................................................................................................. 88
Figure 19. Relationship Between 8.192 Mbits/s and 16.384 Mbits/s Time Slots ................................................... 89
Figure 20. Interrupt Controller .............................................................................................................................. 103
Figure 21. Microprocessor Programming—Reset Page Command ..................................................................... 114
Figure 22. Microprocessor Programming—Make/Break/Query Telephony Connections..................................... 114
Figure 23. T8110L Data Memory Map and Configurations .................................................................................. 116
Figure 24. TDM Data Stream Bit Rates ............................................................................................................... 118
Figure 25. Subrate Switching Example, Byte Packing ......................................................................................... 121
Figure 26. Subrate Switching Example, Byte Unpacking ..................................................................................... 123
Figure 27. Clock Alignment .................................................................................................................................. 129
Figure 28. Frame Timing Diagram ....................................................................................................................... 130
Figure 29. Detailed Clock Skew Timing Diagram................................................................................................. 130
Figure 30. APLL V
Figure 31. T8110L Pins by Functional Group ...................................................................................................... 134
Figure 32. IEEE
Figure 33. Constant Delay Connection Latency................................................................................................... 140
Figure 34. Minimum Delay Connection Latency .................................................................................................. 141
6
T8110L Pull-Up/Pull-Down Arrangement for H1x0 Pins ....................................................................... 20
T8110L Architecture Block Diagram ..................................................................................................... 21
Microprocessor Access Timing, Intel Protocol ...................................................................................... 26
Microprocessor Access Timing, Motorola Protocol ............................................................................... 27
T8110L Main Clocking Paths ................................................................................................................ 44
T8110L NETREF Paths ........................................................................................................................ 44
T8110L Required Frame Pulse and Bit Clock with Polarities ............................................................... 60
T8110L Phase Alignment, SNAP and SLIDE ....................................................................................... 62
Fallback—Fixed vs. Rotating Secondary .............................................................................................. 65
®
1149.1 Boundary-Scan Architecture ........................................................................................ 137
DD
Filtering .............................................................................................................................. 132
List of Figures
Agere Systems Inc.
February 2004
Page