T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 39

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
5 Operating Control and Status
5.2 Error and Status Registers
Status 7, 6, and 3—0 registers are writable by the user for clearing specific error bits. Writing a 1 to any of the bits
of these registers will clear the corresponding error bit. The remaining error and status registers are read-only.
Table 27. Error and Status Register Map
Address
0x0012C
DWORD
(20 bits)
0x00120 Status 3, latched clock
0x00124
0x00128
Device ID, upper
Status 7, system
errors, upper
Reserved
Byte 3
errors
Status 2, latched clock
Device ID, lower
errors, lower
Reserved
Reserved
(continued)
Byte 2
Register
Ambassador T8110L H.100/H.110 Switch
Status 1, transient clock
errors, upper
Reserved
Reserved
Reserved
Byte 1
Status 4 fallback and
clock errors, lower
Status 0, transient
failsafe status
Version ID
Reserved
Byte 0
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