T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 22

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
4 Microprocessor Interface
4.1 Intel/Motorola Protocol Selector
IM_SEL = 1 is the default, if left unconnected, and selects an Intel handshake protocol.
IM_SEL = 0 selects a Motorola handshake protocol.
Note: The IM_SEL signal must be static (either pulled high or pulled low).
Table 9. Intel/Motorola Protocol Selector
4.2 Word/Byte Addressing Selector
WB_SEL = 1 is the default, if left unconnected, and selects 16-bit word aligned addressing.
WB_SEL = 0 selects 8-bit byte aligned addressing.
Note: The WB_SEL signal may be static or dynamic in nature. If dynamic, WB_SEL must follow the same timing
Word-aligned addressing produces 16-bit data transfers via D[15:0]. Byte-aligned addressing produces 8-bit data
transfers via D[7:0] (D[15:8] is unused). The T8110L internal data bus is 32 bits, so A[1:0] address bits are decoded
along with WB_SEL to control a dword-to-word or dword-to-byte swap function back to the data bus.
22
requirements as the address bus.
RDY (DTACK#)
WR# (R/W#)
RD# (DS#)
WB_SEL
IM_SEL
D[15:0]
A[19:0]
Signal
CSN
Intel/Motorola Protocol Selector
WRn (write strobe)
RDn (read strobe)
Intel Mnemonic
D[15:0]
A[15:0]
Default
Default
RDY
CSn
R/Wn (read/write selector)
Motorola Mnemonic
DSn (data strobe)
DTACKn
D[15:0]
A[15:0]
Default
Default
CSn
Agere Systems Inc.
February 2004