T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 25

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
4 Microprocessor Interface
4.3 Access Via the Microprocessor Bus
4.3.1 Microprocessor Interface Register Map (continued)
Table 11. Microprocessor Interface Register Map (continued)
0x006FC
Address
0x0060C
DWORD
(20 bits)
0x00410
0x00420
0x00430
0x00440
0x00450
0x00460
0x00470
0x00474
0x00480
0x00500
0x00600
0x00604
0x00608
0x00610
0x00614
Reference
Cross
12.1
10.1
10.1
10.1
10.1
10.1
10.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.2
7.3
8.1
CLKERR pulse width SYSERR pulse width
FG7 mode upper
System interrupt
CLKERR output
GPIO override
FGIO interrupt
GPIO interrupt
Clock interrupt
enable, upper
enable, upper
Reserved
Reserved
FG1 rate
FG2 rate
FG3 rate
FG4 rate
FG5 rate
FG6 rate
FG7 rate
polarity
polarity
Byte 3
select
(continued)
(continued)
FG7 mode lower
System interrupt
SYSERR output
Clock interrupt
enable, lower
enable, lower
FGIO R/W
GPIO R/W
FG1 width
FG2 width
FG3 width
FG4 width
FG5 width
FG6 width
FG7 width
Reserved
Reserved
Reserved
Byte 2
select
Ambassador T8110L H.100/H.110 Switch
Register
FG7 counter high
FGIO read mask
GPIO read mask
System interrupt
FG1 upper start
FG2 upper start
FG3 upper start
FG4 upper start
FG5 upper start
FG6 upper start
FG7 upper start
In-service, high
pending, upper
pending, upper
FGIO interrupt
GPIO interrupt
Clock interrupt
Reserved
Reserved
Byte 1
enable
enable
byte
FGIO interrupt pend-
GPIO interrupt pend-
Clock interrupt pend-
FGIO data register
GPIO data register
Arbitration control
FG7 counter low
System interrupt
FG1 lower start
FG2 lower start
FG3 lower start
FG4 lower start
FG5 lower start
FG6 lower start
FG7 lower start
pending, lower
In-service, low
ing, lower
Reserved
Byte 0
byte
ing
ing
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