T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 54

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
54
6 Clock Architecture
6.2 Clock Output Control Registers
6.2.1 Master Output Enables Register (continued)
Table 47. Master Output Enables Registers
* Overall selection includes all C clocks OFF, all C clocks ON, or select individual groups of C clocks to be enabled, in conjunction with register
6.2.2 Clock Output Format Registers
The clock output format registers select the pulse width of the /FR_COMP pulse width.
Note: When the T8110L is slowing to a compatibility bus, the /FR_COMP signal must be 122 ns. The T8110L can-
The C8 output rate register selects the CT_C8_A and CT_C8_B clock output frequency 8.192 MHz for ECTF
(H1x0) mode, or 4.096 MHz for MC1 mode.
The SCLK output rate register selects between three SC-Bus clock configurations, including the following:
!
!
!
Byte Address
0x00224.
SCLK = 2.048 MHz, /SCLKx2 = 4.096 MHz
SCLK = 4.096 MHz, /SCLKx2 = 8.192 MHz
SCLK = 8.192 MHz, /SCLKx2 = 8.192 MHz (phase shifted from SCLK)
0x00220
0x00221
0x00224
not phase align to a 244 ns /FR_COMP signal.
Master
Output
Enables
NETREF
Output
Enables
CCLK
Output
Enables
Name
(continued)
Bit(s) Mnemonic
7:4
3:0
7:4
3:0
7:4
3:0
CCOEN
ABOEN
N2OEN
N1OEN
CCSEN
FRSEN
(continued)
Value
0000
0001
0010
0000
0001
0010
0000
0001
0000
0001
0000
0001
0000
0001
0010
0100
0011
0011
Disable A and B clock outputs (default).
Enable A clock outputs only.
Enable B clock outputs only.
Enable both A and B clock outputs.
Disable compatibility (C clock) outputs (default).
Enable C clocks individually*.
Enable all C clocks.
CT_NETREF2 disabled (default).
CT_NETREF2 enabled.
CT_NETREF1 disabled (default).
CT_NETREF1 enabled.
/FR_COMP disabled (default).
/FR_COMP enabled.
C-clock bit clocks disabled (default).
Enable H-MVIP bit clock.
Enable MVIP clocks.
Enable H-MVIP all clocks.
Enable SC-bus clocks.
Function
Agere Systems Inc.
February 2004