T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 3

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Contents
7
8
Agere Systems Inc.
6.2
6.3
6.4
6.5
6.6
6.7
Frame Group and FG I/O ..................................................................................................................................72
7.1
7.2
7.3
7.4
General-Purpose I/O .........................................................................................................................................80
8.1
6.1.10 DPLL2 Input Selector ..................................................................................................................50
6.1.11 NETREF1 Registers....................................................................................................................51
6.1.12 NETREF2 Registers....................................................................................................................52
Clock Output Control Registers ..............................................................................................................53
6.2.1 Master Output Enables Register .................................................................................................53
6.2.2 Clock Output Format Registers...................................................................................................54
6.2.3 TCLK and L_SCx Select Registers .............................................................................................55
Clock Register Access............................................................................................................................57
Clock Circuit Operation—APLL1 ............................................................................................................57
6.4.1 Main Clock Selection, Bit Clock, and Frame ...............................................................................57
6.4.2 Main and Resource Dividers .......................................................................................................61
6.4.3 DPLL1 .........................................................................................................................................61
6.4.4 Reference Selector .....................................................................................................................61
6.4.5 Internal Clock Generation ...........................................................................................................61
Clock Circuit Operation, APLL2 ..............................................................................................................63
6.5.1 DPLL2 .........................................................................................................................................63
Clock Circuit Operation, CT_NETREF Generation.................................................................................63
6.6.1 NETREF Source Select ..............................................................................................................63
6.6.2 NETREF Divider..........................................................................................................................63
Clock Circuit Operation—Fallback and Failsafe .....................................................................................64
6.7.1 Clock Fallback.............................................................................................................................64
6.7.2 Clock Failsafe .............................................................................................................................70
Frame Group Control Registers..............................................................................................................72
7.1.1 FGx Lower and Upper Start Registers ........................................................................................72
7.1.2 FGx Width Registers ...................................................................................................................73
7.1.3 FGx Rate Registers ....................................................................................................................73
FG7 Timer Option ...................................................................................................................................74
7.2.1 FG7 Counter (Low and High Byte) Registers..............................................................................74
FGIO Control Registers ..........................................................................................................................75
7.3.1 FGIO Data Register ....................................................................................................................75
7.3.2 FGIO Read Mask Register..........................................................................................................75
7.3.3 FGIO R/W Register .....................................................................................................................76
FG Circuit Operation...............................................................................................................................77
7.4.1 Frame Group 8 kHz Reference Generation ................................................................................78
7.4.2 FGIO General-Purpose Bits ........................................................................................................79
7.4.3 Programmable Timer (FG7 Only)................................................................................................79
7.4.4 FG External Interrupts.................................................................................................................79
7.4.5 FG Diagnostic Test Point Observation........................................................................................79
GPIO Control Registers ..........................................................................................................................80
6.1.9.1
6.1.10.1 DPLL2 Rate Register...................................................................................................51
6.4.1.1
6.4.1.2
6.4.1.3
6.4.5.1
6.7.1.1
6.7.1.2
6.7.1.3
6.7.2.1
DPLL1 Rate Register...................................................................................................50
Watchdog Timers ........................................................................................................58
Frame Center Sampling ..............................................................................................59
LREF Pair Polarity Configuration.................................................................................60
Phase Alignment .........................................................................................................62
Fallback Events ...........................................................................................................64
Fallback Scenarios—Fixed vs. Rotating Secondary....................................................65
H-Bus Clock Enable/Disable on Fallback ....................................................................68
Failsafe Events ............................................................................................................70
Table of Contents
Ambassador T8110L H.100/H.110 Switch
(continued)
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