T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 104

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
10 Error Reporting and Interrupt Control
10.2 Error Reporting and Interrupt Controller Circuit Operation
10.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0]
Up to 16 of the 48 interrupt inputs are sourced external to the T8110L, via the FG[7:0] and GP[7:0] signals. Each
input is independently controlled via the interrupt control registers (refer to Section 10.1.1 on page 90 and Section
10.1.2 on page 92). Any externally sourced interrupt may be presented as active-high level, active-low level, posi-
tive edge, or negative edge sense. Each external interrupt is maskable. Any detected interrupt which is unmasked
is held in an interrupt pending register, and presented to the arbitration circuit for servicing.
10.2.2 Internally Sourced System Error Interrupts
Another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126—127).
Each of these inputs is independently controlled via the interrupt control registers (refer to Section 10.1.3 on page
93). All internal system error bit interrupts are presented as active-high level sense. Each system error bit interrupt
is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register and presented to the
arbitration circuit for servicing.
10.2.3 Internally Sourced Clock Error Interrupts
Another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits
(0x00122—123; refer to Section 5.2.1 on page 40). Each of these inputs is independently controlled via the inter-
rupt control registers (refer to Section 10.1.6 on page 96). All internal clock error bit interrupts are presented as
active-high level sense. Each clock error bit interrupt is maskable. Any detected interrupt that is unmasked is held
in an interrupt pending register and presented to the arbitration circuit for servicing.
10.2.4 Arbitration of Pending Interrupts
The arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitra-
tion, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. Interrupts are reported
to the system via the SYSERR signal.
10.2.4.1 Arbitration Off
This mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes
place. The trigger for the SYSERR output is simply a logical OR of the internal system error register bits. All bits of
the internal system error register must be cleared in order to rearm the SYSERR trigger in this mode.
10.2.4.2 Flat Arbitration
The flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. When a pending interrupt
wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered,
and that pending bit is cleared, removing it from the next round-robin arbitration cycle. The system must respond to
the current in-service interrupt (refer to Section 10.2.7 on page 105), after which the next arbitration cycle takes
place.
10.2.4.3 Tier Arbitration
The tier arbitration creates three prioritized groups as shown below:
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Highest priority. The 16 internal latched clock error register bits.
Next highest priority. The 16 internal system error register bits.
Lowest priority. The 16 external FG[7:0] and GP[7:0] bits.
(continued)
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Agere Systems Inc.
February 2004