T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 48

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
6 Clock Architecture
6.1 Clock Input Control Registers
6.1.6 Resource Divider Register
The resource divider register contains [divider value – 1]. A value of 0x00 yields a divide-by-1 function. A value of
0xFF yields a divide-by-256 function.
Table 39. Resource Divider Register
6.1.7 Analog PLL2 (APLL2) Rate Register
The APLL2 rate register provides the rate multiplier value to APLL2. When the APLL2 reference clock is at
12.352 MHz, the (times 4) value must be selected. When the APLL2 reference clock is at 6.176 MHz, the
(times 8) value must be selected. A (times 1) value is provided in order to bypass APLL2.
Table 40. APLL2 Rate Register
48
Address
0x00207 APLL2 Rate
Address
0x00205
Byte
Byte
Resource Divider
Name
Name
(continued)
Bit(s) Mnemonic
Bit(s) Mnemonic
7:0
7:0
CKRDR
P2RSR
(continued)
LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256},
Value
0000 0000
0000 0001
0001 xxxx
Value
respectively.
Times 4 (default).
Times 8.
Times 1 BYPASS (lower nibble is don't care).
Function
Function
Agere Systems Inc.
February 2004