T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 130

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
13 Electrical Characteristics
13.6 H-Bus Timing
13.6.1 Timing Diagrams (continued)
Note: Bit 1 is the MSB and Bit 8 is the LSB. MSB is always transmitted first in all transfers.
13.7 ac Electrical Characteristics
13.7.1 Skew Timing, H-Bus
Table 109. Skew Timing, H-Bus
* Test load—50 pF.
† Assumes A and B masters in adjacent slots.
‡ When static skew is 10 ns and in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum
§ Meeting the skew requirements in Table 109 and the requirements of Section 15.5 H-Bus Timing on page 129 could require the PLLs
130
TSKCOMP Maximum Skew Between CT_C8_A and any Compatibility Clock*
skew of 30 ns will occur during that clock cycle.
generating CT_C8 to have different time constants when acting as primary and secondary clock masters.
Symbol
tSKC8
—
/CT_FRAME
Maximum Skew Between CT_C8_A and CT_C8_B*
Maximum Skew Between CT_C8_A and L_SCx Clock*
FRAME BOUNDARY
CT_DX
CT_C8
SLOT
TIME
CT_C8_A
CT_C8_B
(continued)
8
1
Vt+
Figure 29. Detailed Clock Skew Timing Diagram
2
Vt+
3
Figure 28. Frame Timing Diagram
(continued)
4
Parameter
0
tSKC8
5
6
7
COMPATIBILITY
8
CLOCKS
CT_C8_A
125 s
†‡ §
Vt+
1
2
3
Vt+
Vt–
tSKCOMP
tSKCOMP
4
127
Min Typical
—
—
—
5
6
—
—
—
7
Agere Systems Inc.
February 2004
8
±10, ±
1
Max
±5
±2
5-6120F
5-6122F
Unit
ns
ns
ns