T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 50

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
6 Clock Architecture
6.1 Clock Input Control Registers
6.1.9 DPLL1 Input Selector
The DPLL1 input selector selects one of three sources for DPLL1 synchronization input (see Section 6.4.2 on page
61), including the following:
!
!
!
6.1.9.1 DPLL1 Rate Register
The DPLL1 rate register controls the DPLL1 output frequency.
Table 42. DPLL1 Input Selector Registers
6.1.10 DPLL2 Input Selector
The DPLL2 input selector selects one of five sources for DPLL2 synchronization input (see Section 6.5.1 on page
63), including the following:
!
!
!
!
!
50
Address
0x0020A DPLL1 Input Selector
0x0020B DPLL1 Rate
Main clock selection CLK SEL MUX output
Main divider output
Resource divider output
Main clock selection CLK SEL MUX output
Main divider output
Resource divider output
Internal frame
External input via PRI_REF_IN signal
Byte
Name
(continued)
Bit(s) Mnemonic
7:0
7:0
(continued)
D1RSR
D1ISR
0000 0000
0000 0001
0000 0010
0000 0000
0000 0001
Value
Main selector (default).
Main divider.
Resource divider.
DPLL1 output at 4.096 MHz (default).
DPLL1 output at 2.048 MHz.
Function
Agere Systems Inc.
February 2004