T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 61

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.4 Clock Circuit Operation—APLL1
6.4.2 Main and Resource Dividers
Two independently programmable dividers are available to divide down the main clock selection signal. The func-
tion ranges from divide-by-1 (bypass) to divide-by-256.
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Output of both dividers is available to the DPLL1 and the APLL1 reference selector. The output of the main divider
is also available at the PRI_REF_OUT chip output.
Both dividers are reset whenever a changeover between X and Y clock register sets is detected; see Section 6.3
on page 57. This allows for immediate loading of the newly activated divider register values.
6.4.3 DPLL1
A digital phase-lock loop is provided to generate a 4.096 MHz or 2.048 MHz reference to APLL1, selectable via
register 0x0020B (DPLL1 rate). The DPLL1 operates at 32.768 MHz, derived from the XTAL1 crystal input. The
DPLL1 synchronization source is selectable (register 0x0020A, DPLL1 input selector) between the main clock
selection signal, the output of the resource divider, or the output of the main divider, and is intended to be pre-
sented as an 8 kHz frame reference. DPLL1 is determined to be in-lock or out-of-lock, based on the state of the
output clock when an edge transition is detected at the synchronization source. An out-of-lock condition results in a
DPLL1 correction, which can either lengthen or shorten its current output clock period by 30.5 ns.
6.4.4 Reference Selector
The APLL1 reference clock is selectable between five possible sources via register 0x00202, APLL1 input selector.
A 4.096 MHz or 2.048 MHz reference must be provided. The five possible sources are shown below:
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6.4.5 Internal Clock Generation
The main internal functions of T8110L are synchronous to the 65.536 MHz output of APLL1. This clock is further
divided to generate 32.768 MHz, 16.384 MHz, and 8 kHz internal reference signals. Additional divide-down values
to 8.192 MHz, 4.096 MHz, and 2.048 MHz are generated. These generated clocks are the source for H1x0,
H-MVIP, MVIP, and SC-bus clocks when the T8110L is mastering the bus clocks; see Section 6.2 on page 53.
These internally generated clocks can either be free-running, or can be aligned to the incoming main selection
clock and frame, via a phase alignment circuit (see Section 7.4.5.1).
For binary divider values of 1, 2, 4, 8, 16, 32, 64, 128, and 256, the output is 50% duty cycle.
For a divider value of 193, the output is almost 50% duty cycle (low-level duration is one clock cycle shorter than
high-level duration).
For all other divider values, the output is a pulse whose width is one full period of the main clock selection signal.
XTAL1 crystal (16.384 MHz) divided-by-4
Main divider output
Resource divider output
DPLL1 output
PRI_REF_IN external chip input
(continued)
(continued)
Ambassador T8110L H.100/H.110 Switch
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