T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 137

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
14 JTAG/Boundary Scan
14.1 The Principle of Boundary-Scan Architecture
Each primary input signal and primary output signal is supplemented with a multipurpose memory element called a
boundary-scan cell. Cells on device primary inputs are referred to as input cells and cells on primary outputs are
referred to as output cells. Input and output is relative to the core logic of the device.
At any time, only one register can be connected from TDI to TDO. For example, instruction register (IR), bypass,
boundary-scan, ident, or even some appropriate register internal to the core logic (see Figure 32). The selected
register is identified by the decoded output of the instruction register. Certain instructions are mandatory, such as
EXTEST (boundary-scan register selected), whereas others are optional, such as the IDCODE instruction (Ident
register selected).
Figure 32 shows the following elements:
!
!
!
!
!
!
A set of four dedicated test pins, test data in (TDI), test mode select (TMS), test clock (TCK), test data out (TDO),
and one optional test pin test reset (TRSTN). These pins are collectively referred to as the test access port
(TAP).
A boundary-scan cell on each device’s primary input and primary output pin, connected internally to form a serial
boundary-scan register (boundary scan).
A finite-state machine TAP controller with inputs TCK and TMS.
An n-bit (n = 3) instruction register (IR), holding the current instruction.
A 1-bit bypass register (BYPASS).
An optional 32-bit identification register (ident) capable of being loaded with a permanent device identification
code.
TEST MODE SELECT
Figure 32. IEEE
TEST CLOCK
TEST DATA IN
TDI
®
1149.1 Boundary-Scan Architecture
INSTRUCTION REGISTER (IR)
IDENTIFICATION REGISTER
TEST RESET (TRSTN)
CORE LOGIC
TMS
TCK
INTERNAL
Ambassador T8110L H.100/H.110 Switch
BYPASS
TAP
CONTROLLER
TDO
TEST DATA OUT
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