T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 70

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
6 Clock Architecture
6.7 Clock Circuit Operation—Fallback and Failsafe
6.7.2 Clock Failsafe
Clock failsafe provides a safety net for the APLL1 reference clock source and is controlled by three registers,
0x00114—0x00116; see Section 5.1.11 on page 38. A failsafe event overrides the active clock control registers and
forces the APLL1 clock selection to be a fixed 4.096 MHz, derived from the XTAL1 crystal, divided by four. Transi-
tion into one of the failsafe states is independent of clock fallback (i.e., can enter from any state other than INI-
TIAL). Transitions out of the failsafe states are by user command and allow re-entry into either a nonfallback
(primary or secondary) or a fallback (TO_SECONDARY or TO_PRIMARY) state. Refer to Table 56 and Figure 12.
6.7.2.1 Failsafe Events
Clock failsafe (transition from either clock register set to a forced XTAL1-div-4 APLL1 reference clock) can only
occur if the failsafe mode is enabled (register 0x00115, lower nibble), and a failsafe event occurs. A failsafe event
is triggered by a watchdog error on the APLL1 reference clock (i.e., loss-of-reference).
Additionally, an out-of-lock (OOL) condition is provided for debug purposes. This does not trigger a failsafe event,
but does indicate potential difficulty with the APLL1. A lock status flag is provided out of APLL1, and the OOL is
defined by exceeding a user-defined threshold value (register 0x00116). The lock status is a flag indicating when
APLL1 is making a correction to maintain synchronization. The flag is continuously sampled. If enough active flags
are sampled in a row to exceed the user-defined threshold, this condition is reported via the system status register
(0x00125).
70
(continued)
FAILSAFE RETURN TO
FALLBACK STATE
FAILSAFE RETURN TO
FALLBACK STATE
FAILSAFE ENABLED AND
FAILSAFE EVENT
FAILSAFE ENABLED AND
FAILSAFE EVENT
SECONDARY
Figure 12. T8110L Clock Failsafe States
MODE
FIXED
FS_1
FS_2
FAILSAFE ENABLED AND
FAILSAFE EVENT
FAILSAFE ENABLED AND
FAILSAFE EVENT
FAILSAFE RETURN TO
NONFALLBACK STATE
FAILSAFE RETURN TO
NONFALLBACK STATE
ASSERT FALLBACK FLAG)
ASSERT FALLBACK FLAG)
(Y IS THE ACTIVE SET)
(X IS THE ACTIVE SET)
(Y IS THE ACTIVE SET)
(Y IS THE ACTIVE SET,
(X IS THE ACTIVE SET,
TO_SECONDARY
SECONDARY
TO_PRIMARY
FALLBACK
PRIMARY
INITIAL
TYPE
?
RESET
USER COMMAND
CLEAR_FALLBACK
ROTATING
SECONDARY
MODE
USER COMMAND
GO_CLOCKS
FALLBACK ENABLED AND
FALLBACK EVENT
FALLBACK ENABLED AND
FALLBACK EVENT
SECONDARY
MODE
FIXED
(continued)
SECONDARY
ROTATING
MODE
FALLBACK
CLEAR_FALLBACK
TYPE
USER COMMAND
?
Agere Systems Inc.
February 2004
5-9421 (F)