T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 47

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.1 Clock Input Control Registers
6.1.4 APLL1 Rate Register
The APLL1 rate register provides the rate multiplier value to APLL1. When APLL1 reference clock is at
4.096 MHz, the [x16 (multiplied by)] value must be selected. When APLL1 reference clock is at 2.048 MHz, the
[x32 (multiplied by)] value must be selected. A [x1 (multiplied by)] value is provided in order to bypass APLL1.
Table 37. APLL1 Rate Register
6.1.5 Main Inversion Select Register
The main inversion select register controls programmable inversions at various points within the T8110L main
clocking paths and NETREF paths. Internal points allowed for programmable inversion include the following:
!
!
!
!
!
Table 38. Main Inversion Select Register
Address
Address
0x00203 APLL1 Rate
0x00204 Main Inversion Select
Main clock selection CLK SEL MUX output; see Figure 5 on page 44.
NETREF2 divider output; see Figure 6 on page 44.
NETREF2 selection MUX output.
NETREF1 divider output.
NETREF1 selection MUX output.
Byte
Byte
Name
Name
(continued)
Bit(s) Mnemonic
7:0
Bit(s) Mnemonic
7:5
4
3
2
1
0
P1RSR
(continued)
Reserved
N2DSB
N1DSB
N2SSB
N1SSB
ICMSB
0000 0000
0000 0001
0001 xxxx
Value
Value
000
0
1
0
1
0
1
0
1
0
1
Ambassador T8110L H.100/H.110 Switch
Times 16 (default).
Times 32.
Times 1 BYPASS (lower nibble is don't care).
Don't invert main clock selection (default).
Invert main clock selection.
Don't invert NETREF2 divider output (default).
Invert NETREF2 divider output.
Don't invert NETREF2 selection (default).
Invert NETREF2 selection.
Don't invert NETREF1 divider output (default).
Invert NETREF1 divider output.
Don't invert NETREF1 selection (default).
Invert NETREF1 selection.
NOP (default).
Function
Function
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