T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 63

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
6 Clock Architecture
6.5 Clock Circuit Operation, APLL2
APLL2 requires either a 6.176 MHz or 12.352 MHz reference clock to produce a 49.408 MHz clock for operating
DPLL2. A user-supplied rate multiplier (register 0x00207, APLL2 rate) provides either a times 8 function (when ref-
erence clock = 6.176 MHz) or a times 4 function (when reference clock = 12.352 MHz). Additionally, APLL2 may be
bypassed for circuit diagnostic purposes (see Figure 5 on page 44).
6.5.1 DPLL2
A second digital phase-lock loop is provided to generate various derivations of T1 operating frequencies, available
by selection via the TCLK_OUT output. The possible output frequencies are selectable via register 0x0020F
(DPLL2 rate) and include 1.544 MHz, 3.088 MHz, 6.176 MHz, and 12.352 MHz. The DPLL2 input clock operates at
49.408 MHz from the APLL2 output. Synchronization sources for DPLL2 include the same sources provided to
DPLL1 (selectable between the main clock selection signal, the output of the resource divider, or the output of the
main divider) and two additional sources, including the T8110L internally generated frame signal and the
PRI_REF_IN input. These selections are available via register 0x0020E, DPLL2 input selector. DPLL2 is deter-
mined to be in-lock or out-of-lock based on the state of its output when an edge transition is detected at the syn-
chronization source. An out-of-lock condition results in a DPLL2 correction, which can either lengthen or shorten its
current output clock period by 20.2 ns.
6.6 Clock Circuit Operation, CT_NETREF Generation
The T8110L provides two independently programmable paths to generate CT_NETREF1 and CT_NETREF2, via
registers 0x00210—0x00216. Each CT_NETREF is individually enabled with register 0x00221, NETREF output
enables. Each path consists of a source selector MUX and a divider circuit (see Figure 6 on page 44).
6.6.1 NETREF Source Select
XTAL1 input DIV 8 (2.048 MHz)
XTAL1 input (16.384 MHz)
XTAL2 input (6.176 MHz or 12.352 MHz)
LREF[7:0]
CT_NETREFx (the other NETREF—i.e., CT_NETREF1 can be derived from CT_NETREF2, and vise-versa).
The output of the source select MUX is made available directly to the NETREF divider, and also to chip output
(NR1_SEL_OUT, NR2_SEL_OUT).
6.6.2 NETREF Divider
Each NETREF path provides a divider from a divide-by-1 function up to a divide-by-256 function. The clock source
for the divider is selectable between the output of the source select MUX or from external chip input (NR1_DIV_IN,
NR2_DIV_IN).
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The NETREF dividers are reset whenever a changeover between X and Y clock register sets is detected (see Sec-
tion 6.3 on page 57). This allows for immediate loading of the newly activated divider register values.
For binary divider values of 1, 2, 4, 8, 16, 32, 64, and 128, output is 50% duty cycle.
For divider values of 256, 193, plus all other nonbinary values, output is a pulse whose width is one-half of a
clock period, asserted during the second half of the divider clock period.
(continued)
Ambassador T8110L H.100/H.110 Switch
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