T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 113

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

February 2004
Agere Systems Inc.
12 Connection Control
12.1 Programming Interface
Programming the T8110L for time-slot switching requires specific access cycles to the connection memory
regions. Access to other regions (data memory or registers) is made through a standard direct access via the inter-
face.
12.1.1 Connection Memory Programming
Because the microprocessor interface only allows word or byte accesses, multiple write accesses must occur. For
byte access, there are a total of three byte-wide holding registers. For word access, there is one word-wide holding
register. The user must load the holding registers with the proper information first, and then write to the upper byte
(or upper word) to actually move data into the connection memory; refer to Table 95.
The connection memory is divided into four 2K regions, each of which handles up to 128 time slots worth of con-
nectivity for each of 16 serial data streams. The regions include H1x0 even streams (CT_D[30, 28, . . . 0]), H1x0
odd streams (CT_D[31, 29, . . . 1]), local low streams (L_D[15:0]), and local high streams (L_D[31:16]). The con-
nection memory locations are addressed relative to time slot and stream.
Connection memory commands are as follows:
!
!
The MAKE and BREAK commands are presented as multiple microprocessor write cycles. The QUERY command
is presented as multiple microprocessor read cycles; refer to Table 95.
Table 95. Microprocessor Programming, Connection Memory Access
Note: Data byte n required information is shown in Figure 22.
RESET PAGE resets any (up to all four) connection memory region (see Figure 21 on page 114). Address bit 15
determines whether or not it's a reset page command. The reset page command relies on a valid internal chip
clock and loops through all addresses within the connection memory region, resetting the VALID bit field. The
RESET PAGE command is presented as either two microprocessor WORD writes, or four microprocessor BYTE
writes, see Table 95.
MAKE/BREAK/QUERY, telephony connection (see Figure 22 on page 114).
Word/Byte
(WB_SEL)
Word
Word
Byte
Byte
Byte
Byte
A[1:0]
0X
1X
00
01
10
11
Data byte 1
Data byte 3
D[15:8]
X
X
X
X
Data byte 0 Write data byte 0 to a holding register, or read data byte
Data byte 1 Write data byte 1 to a holding register, or read data byte
Data byte 2 Write data byte 2 to a holding register, or read data byte
Data byte 3 Write data byte 3 plus the holding register data to con-
Data byte 0 Write data bytes 1 and 0 to a holding register, or read
Data byte 2 Write data bytes 3 and 2 plus the holding register data
D[7:0]
0 information.
1 information.
2 information.
nection memory, or read data byte 3 information.
data bytes 1 and 0 information.
to connection memory, or read data bytes 3 and 2 infor-
mation.
Ambassador T8110L H.100/H.110 Switch
Access Description
113