AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 83

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.8
8.5
32099F–11/2010
Flash Commands
Writing Words to a Page that is not Completely Erased
The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page write,
or before the page buffer is loaded with data to be stored to the flash page.
This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an
entire page. Note that “one word” for the FLASCHDW is actually 64 bits. Only words that are in a
completely erased state (0xFFFFFFFFFFFFFFFF) can be changed. The procedure is as
follows:
The FLASHCDW offers a command set to manage programming of the flash memory, locking
and unlocking of regions, and full flash erasing. See
commands.
To run a command, the CMD field in the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY bit in the Flash
Status Register (FSR) is automatically cleared. Once the current command is complete, the
FSR.FRDY bit is automatically set. If an interrupt has been enabled by writing a one to
FCR.FRDY, the interrupt request line of the Flash Controller is activated. All flash commands
except for Quick Page Read (QPR) will generate an interrupt request upon completion if
FCR.FRDY is one.
Any HSB bus transfers attempting to read flash memory when the FLASHCDW is busy execut-
ing a flash command will be stalled, and allowed to continue when the flash command is
complete.
After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by poll-
ing the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command
written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHCDW
is IDLE. The user must make sure that the access pattern to the FLASHCDW HSB interface
contains an IDLE cycle so that the command is allowed to start. Make sure that no bus masters
such as DMA controllers are performing endless burst transfers from the flash. Also, make sure
that the CPU does not perform endless burst transfers from flash. This is done by letting the
CPU enter sleep mode after writing to FCMD, or by polling FSR for command completion. This
polling will result in an access pattern with IDLE HSB cycles.
All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the FCMD register. Writing FCMD with data that does not contain the correct key
and/or with an invalid command has no effect on the flash memory; however, the PROGE bit is
set in the Flash Status Register (FSR). This bit is automatically cleared by a read access to the
FSR register.
1. Clear page buffer.
2. Write to the page buffer the result of the logical bitwise AND operation between the
3. Write Page.
contents of the flash page and the new data to write. Only bits that were in an erased
state can be changed from the original page.
AT32UC3L016/32/64
Section 8.8.2
for a complete list of
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