AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 364

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 19-3. Fractional Baud Rate Generator
19.6.1.4
32099F–11/2010
CLK_USART/DIV
CLK
CLK_USART
Reserved
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
1
2
3
0
(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock
divider. This feature is only available when using USART normal mode. The fractional Baud
Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART CLK pin. No division is active. The value written in BRGR
has no effect. The external clock frequency must be at least 4.5 times lower than the system
clock.
When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected,
the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on
the CLK pin. If the internal clock CLK_USART is selected, the Baud Rate Generator ensures a
50:50 duty cycle on the CLK pin, even if the value programmed in CD is odd.
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- -
⎛
⎝
8 2 Over
Modulus
=
Control
(
FP
SelectedClock
------------------------------------- -
SelectedClock
–
CD
) CD
⎛
⎝
+
glitch-free
USCLKS = 3
FP
------ -
logic
FP
8
⎞
⎠
⎞
⎠
SYNC
0
>1
CD
0
1
0
1
AT32UC3L016/32/64
OVER
Sampling
Divider
FIDI
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
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