AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 433

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.3.3
20.7.3.4
Figure 20-7. Programmable Delays
32099F–11/2010
Chip Select 1
Chip Select 2
Clock generation
Transfer delays
SPCK
The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255.
This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud
rate of CLK_SPI divided by 255.
Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbid-
den. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results.
At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing
the first transfer.
The divisor can be defined independently for each chip select, as it has to be configured in the
CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced
peripheral without reprogramming.
Figure 20-7 on page 433
same chip select. Three delays can be configured to modify the transfer waveforms:
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
• The delay between chip selects, programmable only once for all the chip selects by writing to
• The delay before SPCK, independently programmable for each chip select by writing the
• The delay between consecutive transfers, independently programmable for each chip select
the Delay Between Chip Selects field in the MR register (MR.DLYBCS). Allows insertion of a
delay between release of one chip select and before assertion of a new one.
Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to
be delayed after the chip select has been asserted.
by writing the Delay Between Consecutive Transfers field in the CSRn registers
(CSRn.DLYBCT). Allows insertion of a delay between two transfers occurring on the same
chip select
DLYBCS
DLYBS
shows a chip select transfer change and consecutive transfers on the
DLYBCT
AT32UC3L016/32/64
DLYBCT
433