AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 289
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 289 of 858
- Download datasheet (13Mb)
16. External Interrupt Controller (EIC)
16.1
16.2
16.3
Figure 16-1. EIC Block Diagram
32099F–11/2010
E X T IN T n
N M I
Features
Overview
Block Diagram
C L K _ S Y N C
E n a b le
C T R L
D IS
E N
Rev: 3.0.1.0
•
•
•
•
•
•
•
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked. Each external
interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt
input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can
also be configured to be asynchronous in order to wake up the part from sleep modes where the
CLK_SYNC clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode,
code execution starts from the instruction following the sleep instruction.
Dedicated interrupt request for each interrupt
Individually maskable interrupts
Interrupt on rising or falling edge
Interrupt on high or low level
Asynchronous interrupts for sleep modes without clock
Filtering of interrupt lines
Non-Maskable NMI interrupt
F IL T E R
F ilte r
P o la rity
co n tro l
L E V E L
M O D E
E D G E
E d g e/L e ve l
D e te cto r
L E V E L
M O D E
E D G E
A syn ch ro n u s
d e te cto r
A S Y N C
IN T n
C T R L
IC R
IS R
AT32UC3L016/32/64
d e te ct
W a ke
M a sk
IM R
IE R
ID R
E IC _ W A K E
IR Q n
289
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