AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 824

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

35.1.12
35.1.13
35.1.14
35.1.15
32099F–11/2010
aWire
ADCIFB
Chip
I/O Pins
1. aWire CPU clock speed robustness
2. The aWire debug interface is reset after leaving Shutdown mode
1. Using STARTUPTIME value larger than 0x1F will freeze ADC
2. ADCIFB DMA transfers does not work with divided PBA clock
1. Increased Power Consumption in VDDIO in sleep modes
1. PA17 has low ESD tolerance
1000Ohm times the value of the of the sense capacitor instead of a very small resistance
times the value of the sense capacitor.
The aWire memory speed request command counter wraps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the device receives a wake-up either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register
(ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register
(SR.BUSY) will never be cleared.
Fix/Workaround
Do not write values larger than 0x1F to ACR.STARTUP.
DMA requests from the ADCIFB will not be performed when the PBA clock is slower than
the HSB clock.
Fix/Workaround
None
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Solution 1: Disable the OSC0 by writing a zero to the Oscillator Enable bit in the System
Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before
going to any sleep mode where the OSC0 is disabled
Solution 2: Pull down or up XIN0 and XOUT0 with 1MOhm resistor.
PA17 only tolerates 500V ESD pulses (Human Body Model).
Fix/Workaround
Care must be taken during manufacturing and PCB design.
AT32UC3L016/32/64
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