AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 186

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.2
13.5.3
32099F–11/2010
32KHz Oscillator (OSC32K) Operation
Digital Frequency Locked Loop (DFLL) Operation
The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks
propagate to the digital logic.
The OSCn Ready bit (OSCnRDY) in the Power and Clock Status Register (PCLKSR) is set
when the oscillator is stable and ready to be used as clock source. An interrupt can be gener-
ated on a zero-to-one transition on OSCnRDY.
Rev: 1.0.1.0
The 32KHz oscillator operates as described for the oscillator above. The 32KHz oscillator can
be used as source clock for the Asynchronous Timer (AST) and the Watchdog Timer (WDT).
The 32KHz oscillator can be used as source for the generic clocks.
The oscillator is disabled by default after reset. When the oscillator is disabled, the XIN32 and
XOUT32 pins can be used as general-purpose I/Os. When the oscillator is configured to use an
external clock, the clock must be applied to the XIN32 pin while the XOUT32 pin can be used as
general-purpose I/O.
The oscillator is enabled writing a one to the OSC32 Enable bit (OSC32EN) bit in the 32 KHz
Oscillator Control Register (OSCCTRL32). Operation mode (external clock or crystal) is chosen
by writing to the Oscillator Mode (MODE) bit in OSCCTRL32. The oscillator is an ultra-low-
power design and remains enabled in all sleep modes.
The start-up time of the 32KHz oscillator is selected by writing to the Oscillator Start-up Time
field (STARTUP) in the OSCCTRL32 register. The SCIF masks the oscillator output during the
start-up time, to ensure that no unstable clock cycles propagate to the digital logic.
The OSC32 Ready bit (OSC32RDY) in the Power and Clock Status Register (PCLKSR) is set
when the oscillator is stable and ready to be used as clock source. An interrupt can be gener-
ated on a zero-to-one transition on OSC32RDY.
As a crystal oscillator usually requires a very long start-up time (up to 1 second), the 32 KHz
oscillator will keep running across resets, except Power-On-Reset (POR).
The 32KHz oscillator also has a 1KHz output. This is enabled by writing a one to the Enable
1 KHz output bit (EN1K) in OSCCTRL32 register. If the 32KHz output clock is not needed when
1K is enabled, this can be disabled by writing a zero to the Enable 32 KHz output bit (EN32K) in
the OSCCTRL32 register. EN32K is set after a POR.
The 32 KHz oscillator has two possible sets of pins. To select between them write to the Pin
Select bit (PINSEL) in the OSCCTRL32 register. If the 32 KHz oscillator is to be used in Shut-
down mode, PINSEL have to be written to one, and XIN32_2 and XOUT32_2 has to be used.
Rev: 2.0.1.0
The DFLL is controlled by the Digital Frequency Locked Loop Interface (DFLLIF). The DFLL is
disabled by default, but can be enabled to provide a high-frequency source clock for synchro-
nous and generic clocks.
Features:
• Internal oscillator with no external components
AT32UC3L016/32/64
186