AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 515

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.9.1
Name:
Access Type:
Offset:
Reset Value:
• TENBIT: Ten Bit Address Match
• ADR: Slave Address
• SOAM: Stretch Clock on Address Match
• CUP: NBYTES Count Up
• ACK: Slave Receiver Data Phase ACK Value
• PECEN: Packet Error Checking Enable
• SMHH: SMBus Host Header
• SMDA: SMBus Default Address
• SMBALERT: SMBus Alert
32099F–11/2010
SWRST
31
23
15
7
-
Write this bit to zero to disable Ten Bit Address Match.
Write this bit to one to enable Ten Bit Address Match.
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
Writing this bit to zero will not strech bus clock after address match.
Writing this bit to one will strech bus clock after address match.
Writing this bit to zero causes NBYTES to count down (decrement) per byte transferred.
Writing this bit to one causes NBYTES to count up (increment) per byte transferred.
Writing this bit to zero causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
Writing this bit to one causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode.
Writing this bit to zero disables SMBus PEC (CRC) generation and check.
Writing this bit to one enables SMBus PEC (CRC) generation and check.
Writing this bit to zero causes TWIS not to acknowledge the SMBus Host Header.
Writing this bit to one causes TWIS to acknowledge the SMBus Host Header.
Writing this bit to zero causes TWIS not to acknowledge the SMBus Default Address.
Writing this bit to one causes TWIS to acknowledge the SMBus Default Address.
Writing this bit to zero causes TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response
Address (ARA).
Writing this bit to one causes TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address
(ARA).
Control Register
SOAM
30
22
14
6
-
-
CR
Read/Write
0x00
0x00000000
CUP
29
21
13
5
-
-
STREN
ACK
28
20
12
4
-
ADR[7:0]
GCMATCH
PECEN
27
19
11
3
-
SMATCH
TENBIT
SMHH
26
18
10
2
AT32UC3L016/32/64
SMEN
SMDA
25
17
9
1
ADR[9:8]
SMBALERT
SEN
24
16
8
0
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