AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 248

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.3
14.4.4
14.4.5
14.5
14.5.1
14.5.1.1
32099F–11/2010
Functional Description
Interrupts
Peripheral Events
Debug Operation
Initialization
Enabling and disabling the AST clock
In Shutdown mode only the 32 KHz oscillator and the 1KHz clock are available, using certain
pins. Please refer to the Power Manager chapter for details.
The AST interrupt request lines are connected to the interrupt controller. Using the AST inter-
rupts requires the interrupt controller to be programmed first.
The AST peripheral events are connected via the Peripheral Event System. Refer to the Periph-
eral Event System chapter for details.
The AST prescaler and counter is frozen during debug operation, unless the Run In Debug bit in
the Development Control Register is set and the bit corresponding to the AST is set in the
Peripheral Debug Register (PDBG). Please refer to the On-Chip Debug chapter in the
AVR32UC Technical Reference Manual, and the OCD Module Configuration section, for details.
If the AST is configured in a way that requires it to be periodically serviced by the CPU through
interrupts or similar, improper operation or data loss may result during debugging.
Before enabling the AST, the internal AST clock CLK_AST_PRSC must be enabled, following
the procedure specified in
(CLOCK.CSSEL) selects the source for this clock. The Clock Enable bit in the Clock register
(CLOCK.CEN) enables the CLK_AST_PRSC.
When CLK_AST_PRSC is enabled, the AST can be enabled by writing a one to the Enable bit in
the Control Register (CR.EN).
The Clock Source Selection field (CLOCK.CSSEL) and the Clock Enable bit (CLOCK.CEN) can-
not be changed simultaneously. Special procedures must be followed for enabling and disabling
the CLK_AST_PRSC and for changing the source for this clock.
To enable CLK_AST_PRSC:
To disable the clock:
• Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be
• 1KHz clock from the 32KHz oscillator (CLK_1K). This clock is only available in crystal mode,
• Write the selected value to CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a one to CLOCK.CEN, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
enabled before use, and remains enabled in sleep modes when the PB clock is active.
and must be enabled before use.
Section
14.5.1.1. The Clock Source Select field in the Clock register
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