AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 507

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.8.2.4
22.8.2.5
22.8.3
32099F–11/2010
Slave Transmitter Mode
Clock Stretching
Bus Errors
Any slave or bus master taking part in a transfer may extend the TWCK low period at any time.
TWIS may extend the TWCK low period after each byte transfer if CR.STREN=1 and:
If CR.STREN=0 and:
If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set
and TWIS waits for a new START condition.
If TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it
will enter slave transmitter mode and set the SR.TRA bit.
After the address phase, the following actions are performed:
• The address in CR.ADR is checked for address match if CR.SMATCH is set.
• The Alert Response Address is checked for address match if CR.SMAL is set.
• The Default Address is checked for address match if CR.SMDA is set.
• The Host Header Address is checked for address match if CR.SMHH is set.
• Module is in slave transmitter mode, data should be transmitted, but THR is empty, or
• Module is in slave receiver mode, a byte has been received and placed into the internal
• Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains
• Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit
• Module is in slave receiver mode, a byte has been received and placed into the internal
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes
2. Byte to transmit depends on I²C/SMBus mode and CR.PEC:
3. The data byte in the shifter is transmitted.
4. NBYTES is updated. If CR.CUP is set, NBYTES is incremented, otherwise NBYTES
5. After each data byte has been transmitted, the master transmits an ACK (Acknowl-
shifter, but RHR is full, or
stretched until all address match bits in SR have been cleared.
the value present in THR (the last transmitted byte or reset value), and set SR.URUN.
shifter, but RHR is full: Discard the received byte and set SR.ORUN.
to transmit. This is necessary in order to know when to transmit PEC byte. NBYTES
can also be used to count the number of bytes received if using DMA.
– If in I²C mode or CR.PEC=0 or NBYTES!=0: TWIS waits until THR contains a valid
– SMBus mode and CR.PEC=1: If NBYTES=0, the generated PEC byte is
is decremented.
edge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the
SR.NAK bit is changed to one, then the SR.BTF (Byte Transfer Finished) bit is
changed to one. The NAK indicates that the transfer is finished, and TWIS will wait for
a STOP or REPEATED START. If an ACK bit is received, the SR.NAK bit remains at
data byte, possibly stretching the low period of TWCK. After THR contains a valid
data byte, the data byte is transferred to a shifter, and then SR.TXRDY is changed
to one because the THR is empty again.
automatically transmitted instead of a data byte from THR. TWCK will not be
stretched by TWIS.
AT32UC3L016/32/64
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