AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 290

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.6
16.6.1
32099F–11/2010
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Power Management
Clocks
Interrupts
Debug Operation
External Interrupts
Table 16-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines. The
programmer must first program the I/O Controller to assign the desired EIC pins to their periph-
eral function. If I/O lines of the EIC are not used by the application, they can be used for other
purposes by the I/O Controller.
It is only required to enable the EIC inputs actually in use. If an application requires two external
interrupts, then only two I/O lines will be assigned to EIC inputs.
All interrupts are available in all sleep modes as long as the EIC module is powered. However, in
sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous
mode.
The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager.
The filter and synchronous edge/level detector runs on a clock which is stopped in any of the
sleep modes where the system RC oscillator (RCSYS) is not running. This clock is referred to as
CLK_SYNC.
The external interrupt request lines are connected to the interrupt controller. Using the external
interrupts requires the interrupt controller to be programmed first.
Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.
When an external debugger forces the CPU into debug mode, the EIC continues normal opera-
tion. If the EIC is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set
up by the CPU before the interrupts are enabled.
Pin Name
NMI
EXTINTn
I/O Lines Description
Pin Description
Non-Maskable Interrupt
External Interrupt
AT32UC3L016/32/64
Type
Input
Input
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