AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 155

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.3.3
12.6.3.4
12.6.4
12.6.4.1
32099F–11/2010
Shutdown Sleep Mode
SleepWalking
Precautions when entering sleep mode
Description
In all sleep modes where the PBx clocks are stopped, except for Shutdown mode, the chip can
wake partially up if a PBx module asynchronously discovers that it needs its clock. Only the
requested clocks and clock sources needed will be started, and all other clocks will be masked
to zero. E.g. if the main clock source is OSC0, only OSC0 will be started even if other clock
sources were enabled in normal mode. Also generic clocks can be started in a similar way. The
state where only requested clocks are running is referred to as SleepWalking.
The time spent to start the requested clock is mostly limited by the startup time of the given clock
source. This allows PBx modules to handle incoming requests, while still keeping the power con-
sumption at a minimum.
When the chip is SleepWalking any asynchronous interrupt can wake up the chip at any time
without stopping the requested PBx clock.
All requests to start clocks can be masked by writing to the Peripheral Power Control Register
(PPCR), all requests are enabled at reset.
During SleepWalking the interrupt controller clock will be running. If an interrupt is pending when
entering SleepWalking, this will wake up the whole chip.
Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This means that bus transactions are not allowed between clock domains affected
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.
The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.
When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete,
the CPU should perform a read operation from any register on the PB bus before executing the
sleep instruction. This will stall the CPU while waiting for any pending PB operations to
complete.
The Shutdown sleep mode requires extra care. Please refer to
The Shutdown sleep mode is available only when the chip is used in the “3.3V supply mode,
with 1.8V regulated I/O lines“ configuration (see Power Considerations chapter). In this config-
uration, the voltage regulator supplies both VDDCORE and VDDIO power supplies.
When the device enters Shutdown mode, the regulator is turned off and only the following logic
is kept powered by VDDIN:
™
– 2nd 32KHz crystal oscillator (available on PA13/PA20)
AT32UC3L016/32/64
Section
12.6.4.
155