AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 411

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AT32UC3L-EK

Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Datasheets

Specifications of AT32UC3L-EK

Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
32099F–11/2010
LINCE: LIN Checksum Error
LINIPE: LIN Identifier Parity Error
LINISFE: LIN Inconsistent Synch Field Error
LINBE: LIN Bit Error
CTS: Image of CTS Input
CTSIC: Clear to Send Input Change Flag
LINTC: LIN Transfer Completed
LINID: LIN Identifier
NACK: Non Acknowledge
RXBUFF: Reception Buffer Full
ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
TXEMPTY: Transmitter Empty
TIMEOUT: Receiver Time-out
PARE: Parity Error
FRAME: Framing Error
0: No LIN Checksum Error has been detected since the last RSTSTA.
1: A LIN Checksum Error has been detected since the last RSTSTA.
0: No LIN Identifier Parity Error has been detected since the last RSTSTA.
1: A LIN Identifier Parity Error has been detected since the last RSTSTA.
0: No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA
1: The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected since the last
RSTSTA.
0: No Bit Error has been detected since the last RSTSTA.
1: A Bit Error has been detected since the last RSTSTA.
0: CTS is at 0.
1: CTS is at 1.
0: No input change has been detected on the CTS pin since the last read of CSR.
1: At least one input change has been detected on the CTS pin since the last read of CSR.
0: The USART is idle or a LIN transfer is ongoing.
1: A LIN transfer has been completed since the last RSTSTA.
0: No LIN Identifier received or sent
1: The USART is configured as a Slave node and a LIN Identifier has been received or the USART is configured as a Master
node and a LIN Identifier has been sent since the last RSTSTA.
0: No Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
0: The signal Buffer Full from the Receive Peripheral DMA Controller channel is inactive.
1: The signal Buffer Full from the Receive Peripheral DMA Controller channel is active.
If USART does not operate in SPI Slave Mode (MODE … 0xF):
ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA.
ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA.
If USART operates in SPI Slave Mode (MODE = 0xF):
UNRE = 0: No SPI underrun error has occurred since the last RSTSTA.
UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA.
0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in THR, nor in the Transmit Shift Register.
0: There has not been a time-out since the last Start Time-out command (STTTO in CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in CR).
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
0: No stop bit has been detected low since the last RSTSTA.
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