AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 280

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 15-4. Window Mode WDT Timing Diagram
Figure 15-5. Window Mode WDT Timing Diagram, clearing within T
32099F–11/2010
C L R .W D T C L R
W a tc h d o g re s e t
C L R .W D T C L R
W a tch d o g re se t
t= t
t= t
W rite o n e to
W rite o n e to
0
0
The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT
timeout period
where T
bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the
code will start executing form the boot vector, see
will be cleared.
Writing a one to the CLR.WDTCLR bit within the T
counter starts counting from zero (t=t
If the value in the CTRL Register is changed, the WDT counter will be cleared without a watch-
dog reset, regardless of if the value in the WDT counter and the TBAN value.
If the WDT counter reaches T
and the code will start executing form the boot vector.
T
T
tb a n
tb a n
T
timeout
tban
sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR
= T
tban
+ T
psel
= (2
timeout
(TBAN+1)
, the counter will be cleared, the device will receive a reset
0
), entering T
+ 2
(PSEL+1)
tban
, resulting in watchdog reset.
T
T
p s e l
) / f
p se l
tban
psel
Figure 15-5 on page
clk_cnt
, see
period will clear the WDT counter and the
AT32UC3L016/32/64
Figure 15-4 on page
280. The WDT counter
T im e o u t
T im e o u t
280.
280