AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 107

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5.4.1
9.5.5
32099F–11/2010
Interrupts
Operation example
Figure 9-2
als, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU
has been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has
no way of accessing for example the Transmit Holding register in the UART, present on
address X on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs
can be accessed. If for example RTR0 is configured to point to address X, an access to RTR0
will be remapped by the SAU to address X according to the algorithm presented above. By
programming the SAU RTRs, specific addresses in modules that have generally been pro-
tected by the MPU can be performed.
Figure 9-2.
The SAU can generate an interrupt request to signal different events. All events that can gen-
erate an interrupt request have dedicated bits in the Status Register (SR). An interrupt request
will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in
IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER),
and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR).
The interrupt request remains active until the corresponding bit in SR is cleared by writing a
one to the corresponding bit in the Interrupt Clear Register (ICR).
The following SR bits are used for signalling the result of SAU accesses:
• RTR Address Error (RTRADR) is set if an illegal address is written to the RTRs. Only
• Master Interface Bus Error (MBERROR) is set if any of the conditions listed in
addresses in the range 0xFFFC0000-0xFFFFFFFF are allowed.
occurred.
CHANNEL
shows a typical memory map, consisting of some memories, some simple peripher-
CONFIG
UART
SAU
SAU
Example Memory Map for a System with SAU
Transmit Holding
Receive Holding
Channel 1
Baudrate
Control
RTR62
RTR1
RTR0
UR
AT32UC3L016/32/64
Address X
Address Z
Section 9.5.7
107