AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 383

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.6.5.6
Figure 19-21. Header Reception
19.6.5.7
32099F–11/2010
With RSTSTA=1
Write US_CR
Baud Rate
US_LINIR
Clock
LINID
RXD
Header Reception (Slave Node Configuration)
Slave Node Synchronization
All the LIN Frames start with a header which is sent by the master node and consists of a Synch
Break Field, Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At
any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break
Field. As long as a Break Field has not been detected, the USART stays idle and the received
data are not taken in account.
When a Break Field has been detected, the USART expects the Synch Field character to be
0x55. This field is used to update the actual baud rate in order to stay synchronized (see
19.6.5.7). If the received Synch character is not 0x55, an Inconsistent Synch Field error is gen-
erated (see
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier has been received, the flag LINID is set to “1”. At this moment the field
IDCHR in the LIN Identifier register (LINIR) is updated with the received character. The Identifier
parity bits can be automatically computed and checked (see
The synchronization is done only in Slave node configuration. The procedure is based on time
measurement between falling edges of the Synch Field. The falling edges are available in dis-
tances of 2, 4, 6 and 8 bit times.
Figure 19-22. Synch Field
The time measurement is made by a 19-bit counter clocked by the sampling clock (see
19.6.1).
13 dominant bits (at 0)
Break Field
Section
1 recessive bit
19.6.6).
Start
Delimiter
Break
bit
(at 1)
2 Tbit
Start
Bit
1
2 Tbit
0
Synch Byte = 0x55
1
8 Tbit
0
Synch Field
1
0
2 Tbit
1
0
Stop
Bit
Start
AT32UC3L016/32/64
Bit
2 Tbit
ID0 ID1 ID2
Section
ID3
19.6.5.8).
ID4
Stop
bit
ID5
ID6
ID7
Stop
Bit
Section
Section
383