MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 95

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Command and Address Setup, Hold, and Derating
Table 56: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
t
t
t
t
t
IH (base) DC100
IS (base) AC175
IS (base) AC150
IS (base) AC135
IS (base) AC125
Symbol
DDR3-800
200
350
275
–
–
The total
sheet
(page 76)) to the Δ
(page 96)), respectively. Example:
transition, the input signal has to remain above/below V
t
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
tion), a valid input signal is still required to complete the transition and to reach V
V
between the values listed in Table 58 (page 96) and Table 61 (page 98), the derating
values may be obtained by linear interpolation.
Setup (
last crossing of V
for a falling signal is defined as the slew rate between the last crossing of V
the first crossing of V
rate line between the shaded “V
rating value (see Figure 34 (page 99)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded “V
gent line to the actual signal from the AC level to the DC level is used for derating value
(see Figure 36 (page 101)).
Hold (
last crossing of V
for a falling signal is defined as the slew rate between the last crossing of V
the first crossing of V
rate line between the shaded “DC-to-V
rating value (see Figure 35 (page 100)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded “DC-to-V
tangent line to the actual signal from the DC level to the V
ing value (see Figure 37 (page 102)).
VAC (see Table 58 (page 96)).
IL(AC)
DDR3-1066
t
t
IS (base) and
(see Figure 15 (page 48) for input signal requirements). For slew rates which fall
IH) nominal slew rate for a rising signal is defined as the slew rate between the
t
IS) nominal slew rate for a rising signal is defined as the slew rate between the
125
275
200
–
–
t
IS (setup time) and
REF(DC)
IL(DC)max
t
DDR3-1333
IS and Δ
Command and Address Setup, Hold, and Derating
t
IH (base) values (see Table 56; values come from Table 54
IL(AC)max
REF(DC)
190
140
65
–
–
and the first crossing of V
and the first crossing of V
t
. If the actual signal is always later than the nominal slew
IH derating values (see Table 57 (page 96) and Table 58
. If the actual signal is always earlier than the nominal slew
95
t
IH (hold time) required is calculated by adding the data
REF(DC)
DDR3-1600
t
IS (total setup time) =
IH(AC)
170
120
45
–
–
-to-AC region,” use the nominal slew rate for de-
REF(DC)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
/V
REF(DC)
IL(AC)
region,” use the nominal slew rate for de-
1Gb: x4, x8, x16 DDR3 SDRAM
DDR3-1866
at the time of the rising clock transi-
-to-AC region,” the slew rate of a tan-
IH(AC)min
150
100
REF(DC)
65
–
–
REF(DC)
IH(AC)
t
IS (base) + Δ
. Setup (
. Hold (
REF(DC)
region,” the slew rate of a
/V
© 2006 Micron Technology, Inc. All rights reserved.
Units
IL(AC)
ps
ps
ps
ps
ps
level is used for derat-
t
IH) nominal slew rate
t
IS) nominal slew rate
for some time
t
IS. For a valid
V
V
V
V
V
REF(DC)
IH(DC)min
Reference
IH(AC)
IH(AC)
IH(AC)
IH(AC)
IH(DC)
/V
/V
/V
/V
/V
and
IL(AC)
IL(AC)
IL(AC)
IL(AC)
IL(DC)
IH(AC)
and
/