MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 178

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 79: Power-Down Modes
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
DRAM State
Active (any bank open)
Precharged
(all banks precharged)
“Don’t Care”
MR1[12]
exit mode precharge power-down. A summary of the two power-down modes is listed
in Table 79 (page 178).
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out
of power-down mode and go into the reset state. After CKE is registered LOW, CKE
must remain LOW until
power-down duration is
The power-down states are synchronously exited when CKE is registered HIGH (with a
required NOP or DES command). CKE must be maintained HIGH until
satisfied. A valid, executable command may be applied after power-down exit latency,
t
For specific CKE-intensive operations, for example, repeating a power-down exit to re-
fresh to power-down entry sequence, the number of clock cycles between power-down
exit and power-down entry may not be sufficient enough to keep the DLL properly up-
dated. In addition to meeting
power-down exit and power-down entry, two other conditions must be met. First,
must be satisfied before issuing the REFRESH command. Second,
fied before the next power-down may be entered. An example is shown in Figure 107
(page 184).
XP
1
0
t
XPDLL, have been satisfied. A summary of the power-down modes is listed below.
DLL State
Off
On
On
t
PD (MIN) has been satisfied. The maximum time allowed for
t
Down Exit
PD (MAX) (9 ×
Power-
Slow
Fast
Fast
178
t
PD when the REFRESH command is used in between
t
t
t
locked (READ, RDAP, or ODT on)
t
XP to any other valid command
XP to any other valid command
XPDLL to commands that require the DLL to be
XP to any other valid command
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
REFI).
1Gb: x4, x8, x16 DDR3 SDRAM
Relevant Parameters
Power-Down Mode
© 2006 Micron Technology, Inc. All rights reserved.
t
XPDLL must be satis-
t
CKE has been
t
XP